Msg/DevGpio

This page is about the warning messages that can are produced by the GPIO I/O devices. On the Altera University Program computer systems, the same GPIO device is used for switches, push buttons, LEDs, and the 40-pin expansion header.

The GPIO device may not support byte, half-word, or misaligned stores. Use aligned word-sized stores.

The GPIO devices only work correctly with word-sized accesses. Narrower stores produce undefined results.

The GPIO device hardware ignores the byte-enable signals, so the device treats every access as if it were a word-sized access. This is generally ok with loads, because the device replies with the entire 32-bit value and the CPU extracts part of the word for a narrow (16 or 8 bit) load. This fails for narrow stores because the GPIO device will capture all 32 bits of data, but it is not known what the values of the unused data lines are. (It is probably not random, but it is almost certainly not what you want.)

Each bit of the GPIO device's edge capture register is cleared when a 1 is written to the corresponding bit position. Writing 0 does not clear any edge capture register bits.

The edge capture register hardware is designed to clear a bit only when a 1 is written to it.

A long time ago (around Quartus version 13.1 and earlier), writing any value into the edge capture register would clear all bits of the GPIO port's edge capture register. This was changed somewhere around version 14.0 to require writing a 1 to clear (allowing partially clearing the register), but Altera's computer system manuals are still incorrect (as of version 18.0). This warning was added because a non-negligible number of users believed the incorrect documentation and wrote 0 to clear the edge capture register, causing wasted debugging effort.

Disabling this message

This debugging check can be disabled in the Debugging Checks section of the Settings box: Device-specific warnings.