CPUlator Computer System Simulator

CPUlator is a Nios II, ARMv7, MIPS, and RISC-V RV32 simulator of a computer system (processor and I/O devices) and debugger that runs in a modern web browser. It is designed as a tool for learning assembly-language programming and computer organization.

To start using CPUlator now, choose a computer system to simulate, then follow the link.

To learn more, try a sample program in the simulator (Help → Sample programs), or see the documentation.

Features

• Instruction sets: Nios II, ARMv7, MIPS, and RISC-V RV32
• I/O devices:
  • Nios II, ARMv7, and RISC-V: Includes most devices found on a DE1-SoC (and other board models used by the Altera University Program), including interrupt support.
  • MIPS: Includes SPIM-compatible terminal
• Nothing to install: Runs entirely inside a web browser
• Debugger: Single-step, breakpoints, watchpoints, trace, call stack, examine disassembly, memory and registers
• Debug assertions: Optional runtime assertions catch many potential errors
• Input: Accepts both assembly source code and ELF executables
• See more documentation...
• Demo (Nios II program drawing on VGA display)

Nios II, ARMv7, MIPS, and RISC-V Simulator?

It turns out that writing a CPU simulator (or four) is relatively easy. The difficult part is creating a full-featured debugger with a usable and efficient user interface. Thus, CPUlator supports several instruction sets, while reusing the same debugging and UI infrastructure.

The simulator was first written for Nios II in January 2016, for use at the University of Toronto. Support for ARMv7 was added fall 2016, and MIPS32r6 was added in January 2018. MIPS32 release 5 was added November 2018 because it turns out release 6 is incompatible with all earlier MIPS instruction sets, and nobody actually teaches with r6. RISC-V RV32 support was added March 2024, coinciding with the replacement of Nios II with Nios V.

Comparison Chart

The following is a feature comparison of CPUlator with some popular simulators used for teaching.

	CPUlator	MARS 4.5	RARS 1.6	QtSPIM 9.1.20	ARMSim# 2.1
No download/install
Platform	Web browser	Java JRE	Java JRE	Windows, OSX, Linux	.NET 3.0
Free
Open-source
Editor
Code completion				n/a	n/a
Assembler	GNU	custom	custom	custom	GNU
C or other languages
Debugger
Breakpoints
Single-step
Reverse step
Step over function
Step out of function
Modify registers		(except pc/ra)
Modify memory
Show call stack
Runtime calling convention checks
Data watchpoints
Instruction sets	MIPS32 r5 MIPS32 r6 ARMv7 Nios II RV32IMAFD+	MIPS32	RV32/64 IMFDN	MIPS32	ARMv5
Self-modifying code					Partial
MMU
FPU
Memory model	4 GB flat	5 segments	5 segments	5 segments	1 segment
Maximum usable memory	2048 MB	4+4+4 MB data 4+4 MB code	4+4+4 MB data 4+4 MB code	4+1+0.5 MB data 256+64 KB code	96 KB data 512 MB code
I/O devices
Terminal
File I/O
Other devices
Simulation speed (Minst/second)	20	12	0.8	10	1.8