Henry: /* Nios II */

2019-03-11T05:02:33Z

Nios II

← Older revision		Revision as of 05:02, 11 March 2019
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	=== Examples ===		=== Examples ===
	==== Nios II ====		==== Nios II ====
	<syntaxhighlight line lang="Asm">		<syntaxhighlight line lang="Asm" highlight="3,6">
	.global _start		.global _start
	_start:		_start:
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	stw r0, 0(r2) # Write to I/O using stw: Cache bypass should be used for I/O device.		stw r0, 0(r2) # Write to I/O using stw: Cache bypass should be used for I/O device.
	</syntaxhighlight>		</syntaxhighlight>


	=== Debugging ===		=== Debugging ===

Henry: Created page with "Memory accesses to memory-mapped I/O should not be cached (or the devices will not see the memory access), while accesses to regular memory should be cached (cache consistency..."

2019-03-11T05:01:41Z

Created page with "Memory accesses to memory-mapped I/O should not be cached (or the devices will not see the memory access), while accesses to regular memory should be cached (cache consistency..."

New page

Memory accesses to memory-mapped I/O should not be cached (or the devices will not see the memory access), while accesses to regular memory should be cached (cache consistency problems if you bypass the cache and the requested address is in the cache). The Nios II uses software-controlled cache bypass, where the "io" variants of loads and stores (ldwio, stwio) bypass the cache and the regular versions (ldw, stw) do not. This message reports that either a regular load/store was done to an I/O device, or a cache-bypassing load/store was done to regular memory.

=== Examples ===
==== Nios II ====
<syntaxhighlight line lang="Asm">
.global _start
_start:
ldwio r2, 0(r0) # Read memory using ldwio: Cache bypass should not be used for memory.

movhi r2, 0xff20 # DE1-SoC LEDs are at ff200000
stw r0, 0(r2) # Write to I/O using stw: Cache bypass should be used for I/O device.
</syntaxhighlight>

=== Debugging ===
* Check that the load or store is accessing the correct address. If it is, consider whether it is an I/O device or regular memory, and choose the appropriate instruction type.

=== Implementation ===
The simulator knows the memory ranges used by the regular memory devices and I/O devices, and checks that the instruction type used (regular vs. I/O) matches the memory type (regular vs. I/O) at the accessed address. This warning is generated while executing the load or store.

There is some flexibility in interpretation for what can and cannot be safely cached, so there are cases where the memory type assumed by the simulator may be inappropriate. If you're sure that the simulator's expectations do not match reality, you may disable the warning. (An example might be if you want to cache the VGA frame buffer for performance, and then manually flush the data cache at end of drawing each frame.)

It is also possible that you wish the simulator to ignore the cacheability issue entirely, such as if you're using a computer system that does not have a data cache. If so, it is safe to disable this warning. The Altera University Program Nios II computer systems typically do not have a data cache, so the hardware doesn't actually care which instruction you use, but we still taught this concept at the University of Toronto and expected students to choose the right instruction type.

{{DisableMsg|Memory: Suspicious use of cache bypass}}

Msg/MemoryCacheBypass - Revision history

Henry: /* Nios II */

Henry: Created page with "Memory accesses to memory-mapped I/O should not be cached (or the devices will not see the memory access), while accesses to regular memory should be cached (cache consistency..."