Msg/DevGpio - Revision history

Henry at 09:37, 12 March 2019

2019-03-12T09:37:08Z

← Older revision		Revision as of 09:37, 12 March 2019
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	end		end

	...[snip]		//...[snip: Replicate once per edge capture bit]

	always @(posedge clk or negedge reset_n)		always @(posedge clk or negedge reset_n)

Henry at 09:35, 12 March 2019

2019-03-12T09:35:36Z

← Older revision		Revision as of 09:35, 12 March 2019
Line 13:		Line 13:
	A long time ago (around Quartus version 13.1 and earlier), writing any value into the edge capture register would clear all bits of the GPIO port's edge capture register. This was changed somewhere around version 14.0 to require writing a 1 to clear (allowing partially clearing the register), but Altera's computer system manuals are ''still'' incorrect (as of version 18.0). This warning was added because a non-negligible number of users believed the incorrect documentation and wrote 0 to clear the edge capture register, causing wasted debugging effort.		A long time ago (around Quartus version 13.1 and earlier), writing any value into the edge capture register would clear all bits of the GPIO port's edge capture register. This was changed somewhere around version 14.0 to require writing a 1 to clear (allowing partially clearing the register), but Altera's computer system manuals are ''still'' incorrect (as of version 18.0). This warning was added because a non-negligible number of users believed the incorrect documentation and wrote 0 to clear the edge capture register, causing wasted debugging effort.

	Here's a snippet of Verilog code ~~from one bit slice of the edge capture register~~ from the GPIO port device (comments added by me):		Here's a snippet of Verilog code from the GPIO port device (comments added by me), showing the behaviour of one bit slice of the edge capture register:
	<syntaxhighlight line lang="Verilog" highlight="8,9">		<syntaxhighlight line lang="Verilog" highlight="8,9">
	assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);		assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);

Henry: /* Each bit of the GPIO device's edge capture register is cleared when a 1 is written to the corresponding bit position. Writing 0 does not clear any edge capture register bits. */

2019-03-12T09:34:44Z

Each bit of the GPIO device's edge capture register is cleared when a 1 is written to the corresponding bit position. Writing 0 does not clear any edge capture register bits.

← Older revision		Revision as of 09:34, 12 March 2019
Line 12:		Line 12:

	A long time ago (around Quartus version 13.1 and earlier), writing any value into the edge capture register would clear all bits of the GPIO port's edge capture register. This was changed somewhere around version 14.0 to require writing a 1 to clear (allowing partially clearing the register), but Altera's computer system manuals are ''still'' incorrect (as of version 18.0). This warning was added because a non-negligible number of users believed the incorrect documentation and wrote 0 to clear the edge capture register, causing wasted debugging effort.		A long time ago (around Quartus version 13.1 and earlier), writing any value into the edge capture register would clear all bits of the GPIO port's edge capture register. This was changed somewhere around version 14.0 to require writing a 1 to clear (allowing partially clearing the register), but Altera's computer system manuals are ''still'' incorrect (as of version 18.0). This warning was added because a non-negligible number of users believed the incorrect documentation and wrote 0 to clear the edge capture register, causing wasted debugging effort.

			Here's a snippet of Verilog code from one bit slice of the edge capture register from the GPIO port device (comments added by me):
			<syntaxhighlight line lang="Verilog" highlight="8,9">
			assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);

			always @(posedge clk or negedge reset_n)
			begin
			if (reset_n == 0)
			edge_capture[0] <= 0;
			else if (clk_en)
			if (edge_capture_wr_strobe && writedata[0]) // When writing a 1, clear the edge capture bit.
			edge_capture[0] <= 0;
			else if (edge_detect[0]) // When an edge is detected, set the edge capture bit.
			edge_capture[0] <= -1;
			end

			...[snip]

			always @(posedge clk or negedge reset_n)
			begin
			if (reset_n == 0)
			begin
			d1_data_in <= 0;
			d2_data_in <= 0;
			end
			else if (clk_en)
			begin
			d1_data_in <= data_in;
			d2_data_in <= d1_data_in; // Two cycles of past history for the data inputs
			end
			end

			assign edge_detect = ~d1_data_in & d2_data_in; // two_cycles_ago=1 and one_cycle_ago=0 is an "edge".
			</syntaxhighlight>


	{{DisableMsg\|Device-specific warnings}}		{{DisableMsg\|Device-specific warnings}}

Henry: Created page with "This page is about the warning messages that can are produced by the GPIO I/O devices. On the Altera University Program computer systems, the same GPIO device is used for swit..."

2019-03-12T09:30:39Z

Created page with "This page is about the warning messages that can are produced by the GPIO I/O devices. On the Altera University Program computer systems, the same GPIO device is used for swit..."

New page

This page is about the warning messages that can are produced by the GPIO I/O devices. On the Altera University Program computer systems, the same GPIO device is used for switches, push buttons, LEDs, and the 40-pin expansion header.

==== The GPIO device may not support byte, half-word, or misaligned stores. Use aligned word-sized stores. ====

The GPIO devices only work correctly with word-sized accesses. Narrower stores produce undefined results.

The GPIO device hardware ignores the byte-enable signals, so the device treats every access as if it were a word-sized access. This is generally ok with loads, because the device replies with the entire 32-bit value and the CPU extracts part of the word for a narrow (16 or 8 bit) load. This fails for narrow stores because the GPIO device will capture all 32 bits of data, but it is not known what the values of the unused data lines are. (It is probably not random, but it is almost certainly not what you want.)

==== Each bit of the GPIO device's edge capture register is cleared when a 1 is written to the corresponding bit position. Writing 0 does not clear any edge capture register bits. ====

The edge capture register hardware is designed to clear a bit only when a 1 is written to it.

A long time ago (around Quartus version 13.1 and earlier), writing any value into the edge capture register would clear all bits of the GPIO port's edge capture register. This was changed somewhere around version 14.0 to require writing a 1 to clear (allowing partially clearing the register), but Altera's computer system manuals are ''still'' incorrect (as of version 18.0). This warning was added because a non-negligible number of users believed the incorrect documentation and wrote 0 to clear the edge capture register, causing wasted debugging effort.

{{DisableMsg|Device-specific warnings}}